Integrated circuits are formed on semiconductor substrates, or wafers. The wafers are then sawed into microelectronic dies (or “dice”), or semiconductor chips, with each die carrying a respective integrated circuit. Each semiconductor chip is mounted to a package, or carrier substrate, which is often mounted to a motherboard and installed in various electronic systems.
In recent years, integrated circuits have become more complicated both in terms of packing density and the variety of device components that are included in a single circuit. As the productivity and performance demands increase, the size of integrated circuits, as well as the semiconductor chips on which they are formed, continues to be reduced. As the individual devices (e.g., transistors) within the integrated circuits become smaller and smaller, integrated circuit designers and manufacturers must constantly overcome various natural phenomena and limitations due to the design of, as well as the processing steps used to form, the integrated circuits.
One such phenomenon is known as “hot carrier injection” (HCI). HCI occurs when electrons, or holes, are accelerated by a strong electric field and gain very high kinetic energies within a semiconductor device. The high kinetic energies cause impact ionization on the semiconductor lattice to generate pairs of electrons and holes moving in random directions with high kinetic energies, which are called “hot carriers.” Some of the hot carriers are injected and trapped in a dielectric within the device (e.g., the gate oxide or silicide block), where they form an undesirable space charge, which can cause device degradation and/or instability.
One current approach for minimizing HCI includes forming an “extended drain” (i.e., a lightly-doped drift region between the channel under the gate and the drain outside the gate). However, such structures are not compatible with current submicron processing techniques. More recently, extended drains have been incorporated by forming a silicide block between the gate and the drain with a self-aligned implantation to form the lightly-doped drift region. However, even with low electric fields, the silicide block experiences significant HCI damage, and the charge trapped within the silicide block causes significant transconductance degradation, as well as the linear current degradation. In order to improve the performance of an extended drain device, the doping within the drift region must be extremely low, which increases the parasitic resistance of the device. The problems associated with HCI are exacerbated as devices continue to get smaller while maintaining relatively high operational voltages (e.g., approximately 5 V). Because of the problems caused by HCI, conventional device designs, such as those incorporating the extended drains using silicide blocks, may not perform adequately while incorporating the latest submicron (e.g., 0.13 micron) technology platforms.
Accordingly, it is desirable to provide a semiconductor device with improved HCI immunity. In addition, it is desirable to provide a semiconductor device with increased current carrying capability that can be constructed using the latest complimentary metal oxide semiconductor (CMOS) processing techniques. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.